The present invention relates to a semiconductor device, and more particularly to a dynamic memory semiconductor device including shared sense amplifiers. One known dynamic memory semiconductor device disclosed in Japanese patent application No. 55-41622 has a plurality of sense amplifiers sharing a column decoder circuit which produces a selective signal for controlling switches between the sense amplifiers and data output lines. The area of the dynamic memory semiconductor device is prevented from being increased when implemented in a large-scale configuration because the number of column decoders can be reduced. FIGS. 1 through 5 of the accompanying drawings show the layouts of some conventional semiconductor devices with shared sense amplifiers. The conventional semiconductor devices are classified into several types according to the resistance of the material used of interconnections and the scale of the semiconductor device.
FIG. 1 shows the layout of a first conventional semiconductor device. The conventional semiconductor device shown in FIG. 1 has interconnections made up of three layers, i.e., a polycrystalline silicon layer, a silicide layer, and a metallic layer. More specifically, word lines 401 are formed from the polycrystalline silicon layer and shared by the gate electrodes of MIS (Metal Insulator Semiconductor) transistors of memory cells 402. Bit lines 403 and interconnections (hereinafter referred to as "Y switches") 404 for transmitting selective signals from column decoders are formed from the silicide layer. One Y switch 404 is provided with respect to every four or eight bit lines 403. The metallic layer provides word-backing interconnections 406 disposed on cell arrays 405 for the purpose of virtually reducing the resistance of the word lines 401, array signal lines 408 disposed on sense amplifiers 407 parallel to the word lines 401 for transmitting sense amplifier drive signals or the like, and interconnections in row decoders 409, column decoders 410, array signal drive circuits 411, and peripheral circuits.
FIG. 2 shows the layout of a second conventional semiconductor device. The conventional semiconductor device shown in FIG. 2 has interconnections made up of three layers, i.e., a polycrystalline silicon layer and two metallic layers. Stated otherwise, the semiconductor device shown in FIG. 2 is equivalent to the semiconductor device shown in FIG. 1 where the silicide layer is replaced with a metallic layer. The resistance of Y switches 504 is reduced because they are composed of the metallic layer. Since more sense amplifiers can be connected than in the first conventional semiconductor device, the semiconductor device shown in FIG. 2 is more suitable for large-scale integration.
FIG. 3 shows the layout of a third conventional semiconductor device. The conventional semiconductor device shown in FIG. 3 has interconnections made up of three layers, i.e., a laminated layer of polycrystalline silicon and silicide (hereinafter referred to as a "polycide layer"), a silicide layer, and a metallic layer. More specifically, word lines 601 are formed from the polycide layer and shared by the gate electrodes of MIS transistors of memory cells 602. Y switches 604 are formed from the silicide layer. Bit lines 603, array signal lines 608 disposed on sense amplifiers 607, interconnections in row decoders 609, column decoders 610, array signal drive circuits 611, and peripheral circuits are formed from the metallic layer. Inasmuch as the bit lines and the Y switches are formed from different layers, unlike the first and second conventional semiconductor devices, if the bit lines are fabricated by the same process, they can be narrowed in the absence of any Y switches in their layer, resulting in a reduction in the size of the memory cell arrays. Furthermore, since the Y switches 604 are arranged at wide intervals, their width may be greater than in the first conventional semiconductor device, and their resistance may be reduced for a larger storage capacity.
However, the third conventional semiconductor device is less suitable for a larger storage capacity than the second conventional semiconductor device because the Y switches 604 have a greater resistance than those of the metallic layer in the second conventional semiconductor device. In the third conventional semiconductor device, no word-backing interconnections are employed, but the word lines are constructed from the polycide layer for reducing the resistance of the word lines. Consequently, the resistance of the word lines is not lowered as much as for the word lines combined with the word-backing interconnections, and hence the number of cells that can be connected to the word lines cannot be increased.
FIG. 4 shows the layout of a fourth conventional semiconductor device. The conventional semiconductor device shown in FIG. 4 has interconnections made up of four layers, i.e., a polycrystalline silicon layer, a silicide layer, and two metallic layers. The polycrystalline silicon layer may be replaced with a polycide layer. Word lines 701 are formed from the polycrystalline silicon layer or the polycide layer and shared by gate electrodes of MIS transistors of memory cells 702. Bit lines 703 are formed from the silicide layer. One of the metallic layers provides word-backing interconnections 706 disposed on cell arrays 705 parallel to word lines 701, and some interconnections in row decoders 709, column decoders 710, array signal drive circuits 711, and peripheral circuits. The other metallic layer provides Y switches 704 disposed on cell arrays 705 and sense amplifiers 707 perpendicular to word lines 701, and some interconnections in row decoders 709, column decoders 710, array signal drive circuits 711, and peripheral circuits. Since Y switches 704 and word-backing interconnections 706 are made from different metallic layers, the interconnections parallel and perpendicular to word lines 701 have a smaller resistance than those of the first, second, and third conventional semiconductor devices, making the fourth conventional semiconductor device suitable for a large-storage-capacity configuration.
FIG. 5 shows the layout of a fifth conventional semiconductor device. The conventional semiconductor device shown in FIG. 5 has interconnections made up of four layers, i.e., a polycide layer, a silicide layer, and two metallic layers. Word lines 801 are formed from the polycide layer and shared by the gate electrodes of MIS transistors of memory cells 802. Bit lines 803 are formed from the silicide layer. One of the metallic layers provides main word lines 806 disposed on cell arrays 805 parallel to word lines 801, array signal lines 808 disposed on sense amplifiers 807 parallel to word lines 801, and some interconnections in row decoders 809, column decoders 810, array signal drive circuits 811, divided decoders 812, divided decoder drive circuits 813, and peripheral circuits. The other metallic layer provides Y switches 804 disposed on cell arrays 805 and sense amplifiers 807 perpendicularly to word lines 801, divided decoder drive signal lines 814 disposed on divided decoders 812 perpendicular to word lines 801, and some interconnections in row decoders 809, column decoders 810, array signal drive circuits 811, divided decoders 812, divided decoder drive circuits 813, and the peripheral circuits. In the fifth conventional semiconductor device, the word-backing interconnections in the fourth conventional semiconductor device are dispensed with, and some of the row decoders are scattered as divided decoders 812 between cell arrays 805, divided decoders 812 and row decoders 809 are interconnected by main word lines 806, and a signal required to select word lines 801 in divided decoders 812 is received by divided decoder drive circuits 813 and divided decoder drive signal lines 814. For further detail, reference should be made to K. Noda, T. Saeki, A. Tsujimoto, T. Murotani, and K. Koyama, "A Boosted Dual Word-line Decoding Scheme for 256 Mb DRAMs," 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113, and T. Sugibayashi, et. al., "A 30 ns 256 Mb DRAM with Multi-divided Array Structure," 1993 IEEE ISSCC Digest of Technical Papers, pp. 50-51. Since the number of main word lines 806 can be reduced to 1/2.sup.n of the word-backing interconnections, main word lines 806 can be increased in width for reduced resistance, and the fifth conventional semiconductor device is therefore suitable for a large-storage-capacity configuration.
FIG. 6 of the accompanying drawings illustrates the circuit of a conventional sense amplifier region. In the conventional sense amplifier region, bit lines 903 and Y switches 904 lie parallel to each other, and array signal lines 908 including write data lines 921, write drive signal lines 922, read data lines 923, read drive signal lines 924, an N-channel sense amplifier drive signal line 925, and a P-channel sense amplifier drive signal line 926 lie perpendicular to bit lines 903. N-channel sense amplifier drive signal line 925 and P-channel sense amplifier drive signal line 926 are required to be in the form of metallic interconnections because they should be of a low resistance for passing currents for charging and discharging bit lines 903.
In the conventional semiconductor devices described above, since a single column decoder controls a plurality of sense amplifiers with Y switches, the number of column decoders used is lowered to reduce any increase in the area of the semiconductor device which is caused by a large-storage-capacity arrangement thereof. As the storage capacity increases from 1 Mbit to 4 Mbits to 16 Mbits to 64 Mbits, the number of sense amplifiers connected to one column decoder is increased. Therefore, it is necessary to reduce the resistance of the Y switches, and a metallic layer used for only the Y switches is needed on the cell arrays as with the fourth and fifth conventional semiconductor devices described above. The array signal lines on the sense amplifiers must also be formed from a low-resistance metallic layer as they pass a large current therethrough. Consequently, since the Y switches and the array signal lines intersect each other at the sense amplifiers, the fourth and fifth conventional large-storage-capacity semiconductor devices with shared sense amplifiers employ four-layer interconnections other than a conductive layer for forming a capacitor. The process of fabricating such a semiconductor device entails an increased number of steps, and the yield of such a semiconductor device is low.